Regviz

Espressif Systems /ESP32-S3 /RTC_CNTL /INT_ENA_RTC_W1TC

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INT_ENA_RTC_W1TC

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/RTC_CNTL/INT_ENA_RTC_W1TC#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLP_WAKEUP_INT_ENA_W1TC)SLP_WAKEUP_INT_ENA_W1TC 0 (SLP_REJECT_INT_ENA_W1TC)SLP_REJECT_INT_ENA_W1TC 0 (SDIO_IDLE_INT_ENA_W1TC)SDIO_IDLE_INT_ENA_W1TC 0 (WDT_INT_ENA_W1TC)WDT_INT_ENA_W1TC 0 (TOUCH_SCAN_DONE_INT_ENA_W1TC)TOUCH_SCAN_DONE_INT_ENA_W1TC 0 (ULP_CP_INT_ENA_W1TC)ULP_CP_INT_ENA_W1TC 0 (TOUCH_DONE_INT_ENA_W1TC)TOUCH_DONE_INT_ENA_W1TC 0 (TOUCH_ACTIVE_INT_ENA_W1TC)TOUCH_ACTIVE_INT_ENA_W1TC 0 (TOUCH_INACTIVE_INT_ENA_W1TC)TOUCH_INACTIVE_INT_ENA_W1TC 0 (BROWN_OUT_INT_ENA_W1TC)BROWN_OUT_INT_ENA_W1TC 0 (MAIN_TIMER_INT_ENA_W1TC)MAIN_TIMER_INT_ENA_W1TC 0 (SARADC1_INT_ENA_W1TC)SARADC1_INT_ENA_W1TC 0 (TSENS_INT_ENA_W1TC)TSENS_INT_ENA_W1TC 0 (COCPU_INT_ENA_W1TC)COCPU_INT_ENA_W1TC 0 (SARADC2_INT_ENA_W1TC)SARADC2_INT_ENA_W1TC 0 (SWD_INT_ENA_W1TC)SWD_INT_ENA_W1TC 0 (XTAL32K_DEAD_INT_ENA_W1TC)XTAL32K_DEAD_INT_ENA_W1TC 0 (COCPU_TRAP_INT_ENA_W1TC)COCPU_TRAP_INT_ENA_W1TC 0 (TOUCH_TIMEOUT_INT_ENA_W1TC)TOUCH_TIMEOUT_INT_ENA_W1TC 0 (GLITCH_DET_INT_ENA_W1TC)GLITCH_DET_INT_ENA_W1TC 0 (TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC)TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC

Description

oneset clr rtc interrupt enable

Fields

SLP_WAKEUP_INT_ENA_W1TC

enable sleep wakeup interrupt
SLP_REJECT_INT_ENA_W1TC

enable sleep reject interrupt
SDIO_IDLE_INT_ENA_W1TC

enable SDIO idle interrupt
WDT_INT_ENA_W1TC

enable RTC WDT interrupt
TOUCH_SCAN_DONE_INT_ENA_W1TC

enable touch scan done interrupt
ULP_CP_INT_ENA_W1TC

enable ULP-coprocessor interrupt
TOUCH_DONE_INT_ENA_W1TC

enable touch done interrupt
TOUCH_ACTIVE_INT_ENA_W1TC

enable touch active interrupt
TOUCH_INACTIVE_INT_ENA_W1TC

enable touch inactive interrupt
BROWN_OUT_INT_ENA_W1TC

enable brown out interrupt
MAIN_TIMER_INT_ENA_W1TC

enable RTC main timer interrupt
SARADC1_INT_ENA_W1TC

enable saradc1 interrupt
TSENS_INT_ENA_W1TC

enable tsens interrupt
COCPU_INT_ENA_W1TC

enable riscV cocpu interrupt
SARADC2_INT_ENA_W1TC

enable saradc2 interrupt
SWD_INT_ENA_W1TC

enable super watch dog interrupt
XTAL32K_DEAD_INT_ENA_W1TC

enable xtal32k_dead interrupt
COCPU_TRAP_INT_ENA_W1TC

enable cocpu trap interrupt
TOUCH_TIMEOUT_INT_ENA_W1TC

enable touch timeout interrupt
GLITCH_DET_INT_ENA_W1TC

enbale gitch det interrupt
TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC

enbale touch approach_loop done interrupt

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data